1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to a semiconductor memory device in which a memory cell array is divided into a plurality of blocks.
2. Description of the Related Art
In semiconductor memory devices such as DRAMs (Dynamic Random Access Memories) and flash memories, a memory cell array is divided into a plurality of blocks, with peripheral circuits of the memory core such as an X decoder, a Y decoder, and sense amplifiers being provided separately for each block. Such division into blocks brings about advantages such as high-speed data access by reducing the load on the bit lines and word lines.
When a memory cell array is divided into a plurality of blocks, a multiplexer needs to be provided for the purpose of selecting an output of a selected one of the blocks at the time of data reading for supply to an output circuit.
FIG. 1 is a block diagram showing an example of the construction of a related-art semiconductor memory device in which a memory cell block is divided into a plurality of blocks.
The semiconductor memory device of FIG. 1 includes memory cell arrays 11-0 through 11-3, sense amplifiers 12-0 through 12-3, a multiplexer 13, an output circuit 14, a control circuit 15, buffers 16-0 through 16-3, redundancy bit signal lines 17-0 through 17-3, and data signal lines 18-0 through 18-3.
The memory cell arrays 11-0 through 11-3 include memory cells arranged in rows and columns, a plurality of word lines, a plurality of bit lines, an X decoder for selecting a word line, and a Y decoder for selecting a Y address. Data access to the memory cell arrays 11-0 through 11-3 is controlled by the control circuit 15. The sense amplifiers 12-0 through 12-3 are provided for the respective memory cell arrays 11-0 through 11-3, and amplify data read from memory cells. The amplified data is supplied to the multiplexer 13 through the data signal lines 18-0 through 18-3. Similarly, redundancy bit signals read from the memory cell arrays 11-0 through 11-3 are amplified by the respective sense amplifiers 12-0 through 12-3. The amplified signals are then supplied to the multiplexer 13 through the redundancy bit signal lines 17-0 through 17-3. In this example, data signals DSIB(63:0)_n read from each memory cell array 11-n (n=0-3) are comprised of 64 bits, and a redundancy bit signal DSIBRED_n is 1 bit.
The multiplexer 13 decides whether to replace 64-bit of the data signals DSIB(63:0)_n with the redundancy bit DSIBRED_n based on 64-bit redundancy selection signals RED(63:0)_n. Furthermore, the multiplexer 13 selects a read signal that corresponds to one of the memory cell arrays (blocks) 11-0 through 11-3. Such selection is made based on block selection signals MUX_(3:0). This achieves 4-to-1 data selection. Furthermore, the multiplexer 13 selects one of the four pages defined by respective 16-bit subsets of 64 bits based on page selection signals PAGE(3:0). The multiplexer 13 thus supplies 16-bit output data to the output circuit 14.
FIG. 2 is a circuit diagram showing a portion of the multiplexer 13.
The portion of the multiplexer 13 shown in FIG. 2 is a circuit section that performs redundancy bit replacement and page selection. The circuit of FIG. 2 relates to the data signals DSIB(63:0)_0 and the redundancy bit signal DSIBRED_0 supplied from the memory cell array 11-0. A circuit construction the same as that of. FIG. 2 is provided for each of the memory cell array 11-1, the memory cell array 11-2, and the memory cell array 11-3.
The circuit of FIG. 2 includes selector circuits 20-0 through 20-15. The selector circuits 20-0 through 20-15 all have the same circuit construction, and each include transfer gates 21 through 28 and transfer gates 31 through 34, as demonstrably shown in the selector circuit 20-0. Each selector circuit receives 4 consecutive bits of the data signals DSIB(63:0)_0. The transfer gates 21 through 28 are controlled by 4 corresponding bits of the redundancy selection signals RED(63:0)_0. The transfer gates 21 through 28 make a selection as to whether to replace 4 corresponding bits of the data signals DSIB(63:0)_0 with the redundancy bit DSIBRED_0.
Furthermore, the transfer gates 31 through 34 select 1 bit from the 4 corresponding bits having undergone the redundancy processing based on the page selection signals PAGE (3:0). Consequently, the selector circuits 20-0 through 20-15 output signals DSO(0)_0 through DSO(15)_0, respectively. The circuit having the same construction as that of FIG. 2 and corresponding to the memory cell array 11-1 outputs signals DSO(0)_1 through DSO(15)_1. Furthermore, the circuit corresponding to the memory cell array 11-2 outputs signals DSO(0)_2 through DSO(15)_2, and the circuit corresponding to the memory cell array 11-3 outputs signals DSO(0)_3 through DSO(15)_3.
In this manner, redundancy bit replacement and page selection are performed.
FIG. 3 is a circuit diagram showing another portion of the multiplexer 13.
The portion of the multiplexer 13 shown in FIG. 3 is a circuit section that performs block selection. The circuit of FIG. 3 includes selector circuits 40-0 through 40-15. The selector circuits 40-0 through 40-15 all have the same construction, and each include transfer gates 41 through 44, as demonstrably shown in the selector circuit 40-0. A selector circuit 40-m (m=0-15) receives a 1 corresponding bit from each of the four circuits having the construction of FIG. 2 provided for the four respective blocks. That is, a total of 4 bits DSO(m)_0 through DSO(m)_3 are input. The transfer gates 41 through 44 selects one of the four input bits based on the block selection signals MUX_(3:0). As a result, the selector circuits 40-0 through 40-15 output signals DSO (0) through DSO (15), respectively, as signals after block selection.
In this manner, redundancy bit replacement, page selection, and block selection are performed.
Another related-art example is Japanese Patent Application Publication No. 6-150644, which is directed to a data selector that selects data retrieved from the memory block as secondary selection.
In the circuit of FIG. 2, the redundancy bit signal DSIBRED_0 that is a 1-bit signal is input into 64 transfer gates. This means that the load on the redundancy bit signal DSIBRED_n (n=0-3) is heavy, which requires the insertion of a buffer 16-n in the redundancy bit signal line 17-n in order to ensure proper operations, as shown in FIG. 1. The buffer 16-n needs capability to drive 64 signal lines, and is thus a large circuit element occupying a large area.
Further, the distance from each block (the memory cell arrays 11-0 through 11-3) to the multiplexer 13 is long, which gives rise to a problem in that the data signal lines 18-0 through 18-3 end up having the heavy capacitance load, resulting in slower data-read speed of memory cells.
Accordingly, there is a need for a semiconductor memory device which has a reduced circuit size with a construction in which the memory cell array is divided into blocks.
Moreover, there is a need for a semiconductor memory device which has an improved speed of memory cell read operation with a construction in which the memory cell array is divided into blocks.